Tip-offs
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Each week, we surface promising startups & founders through data signals.
This week, we're spotlighting Agentic Design Automation →
Chip design's last manual loop
From tools an engineer drives to agents that close the loop
Agentrys took a 32-bit CPU from specification to a sign-off-clean GDS layout with no human in the loop. On NVIDIA's public CVDP verification benchmark, it is among the first to clear 90%. Cadence bought ChipStack outright.
EDA has automated the individual tasks for thirty years. A human still decides what to run, reads the failure, and writes the fix.
Every AI chip is gated on the same scarce resource: senior verification and physical-design engineers. Chip complexity climbs about 50% a year while design productivity improves about 20%. So the agents are moving from assisting inside the loop to closing it. Mark Ren, who led NVIDIA's ChipNeMo, calls the category agentic design automation.
Agentic Design Automation Startups
Early-stage startups putting agents inside the chip and board design loop, ranked by website visit growth over the past 3 months.
Architect Labs | 636% growth in 3 months
An AI system that designs and verifies custom chips end to end, turning a workload spec into production-ready silicon. Raised a $24M Seed in June 2026.
Palo Alto, US
Diode Computers | 92% growth in 3 months
An AI-native PCB platform that compiles circuit boards from code, with real manufacturing constraints built into the design. Raised an $11.4M Series A in July 2025.
New York, US
atopile | 58% growth in 3 months
A code-first hardware design platform whose own language lets engineers describe, validate, and build circuit boards as version-controlled code. Raised a $125K Pre-Seed in April 2024.
San Francisco, US
Axiomatic AI | 19% growth in 3 months
Frontier models paired with formal mathematical verification, so photonics and electronics designs get proved rather than just generated. Raised an $18M Seed in March 2026.
Boston, US
Bronco AI | 13% growth in 3 months
Agents for design verification that read waveforms, simulation logs, RTL, and UVM testbenches, so chip teams find bugs faster and close the verification gap. Raised a $500K Pre-Seed in September 2023.
San Francisco, US
Agentic Design Automation Founders
Founders attacking the design flow on pre-seed and seed money.
Michael Lazarenko
Co-founder & CEO of Embedd, which builds digital twins of chips and generates the integration code they need to talk to system software. Raised $2.7M Pre-Seed in Aug 2026.
London, UK
Founder & CEO of Tattvam AI, training a reasoning model for timing closure on the RTL-to-GDSII path. Raised $1.7M Pre-Seed in Feb 2026.
London, UK
Ngoc Bach Nguyen
Co-founder of siliXon, which turns a plain-language brief into a complete PCB design, layout and manufacturing files included. Raised $1.5M Pre-Seed in May 2026.
London, UK
Mihailo Isakov
Founder & CEO of BoolSi, a compiler that trains neural networks into pure digital logic, turning a hot C function into a verified FPGA accelerator. Raised $6M Seed in Jun 2026.
Boston, US
Harald Kröll
Co-founder & CEO of Chipmind, whose design-aware agents plug into a team's existing EDA tools and take on the repetitive verification work. Raised $2.5M Pre-Seed in Oct 2025.
Zurich, Switzerland
